Components on a computer chip may be organized as an on-chip network of nodes. For example, a multicore processor may be organized as an on-chip network of cores. High traffic on on-chip networks (e.g., due to traffic bursts) can result in performance decreases, increased power consumption, and decreased quality of service.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.